1. Technical Field
The present invention relates to semiconductor design technology, and more particularly, to a semiconductor device capable of performing a memory test and a semiconductor system including the same.
2. Related Art
In general, a data read operation and a data write operation must be precisely performed in a semiconductor memory device, such as DRAM. To maintain precision, a failed memory cell should not exist in a memory chip. According to the tendency toward high integration of semiconductor technology, the number of memory cells integrated into one memory chip is increasing. Thus, the possibility that a failed memory cell may exist within a chip is increasing despite an advanced fabrication process. If this failed memory cell is not precisely tested, it may lead to deteriorated reliability in a semiconductor memory device.
In a test operation of a semiconductor memory device, if the test operation is performed for each memory cell, the time taken to test a high-integrated semiconductor memory device increases, resulting in increased costs. Accordingly, devices and methods for reducing the time taken to test a semiconductor memory device are desirable.